Method and apparatus for enhancing the performance of semiconductor memory devices
US6026042A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing a peak current produced by the simultaneous activation of numerous sense amplifiers associated with an active word line, without reducing the speed of operation of the semiconductor memory device. A memory array includes word lines accessing memory cells and a tracking word line for sequentially activating the sense amplifiers connected to the digit lines by introducing a delay after the activation of each sense amplifier or group of sense amplifiers and before activating the next sense amplifier or group of sense amplifiers, so that the total time for activation of the sense amplifiers for all digit lines associated with an active word line is spread out, but is not longer than the time necessary for activation of an entire word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.