Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6029250A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1998 |
| Grant date | Feb 22, 2000 |
| Priority date | — |
| Expiry date | Sep 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, and stored in the latch responsive to the clock signal. The digital signal stored in the latch is evaluated to determine if the stored digital signal has an expected value. The timing offset of the digital signal is thereafter adjusted relative to the clock signal. and the digital signal is once again stored in the latch responsive to the clock signal at the new timing offset. A number of digital signals at respective timing offsets relative to the clock signal are stored and evaluated, and a final timing offset of the digital signal is selected from the ones of the timing offsets that cause the latch to store the digital signal having the expected value. The timing offset of the digital signal is thereafter adjusted to the selected final timing offset. A read synchronization circuit may adaptively adjust the timing offset of digital signals in this manner, and such a read synchronization …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.