Self-aligned connector for stacked chip module
US6030855A · kind A · utility
12Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a stack of two semiconductor chips. An edge of the chips forms a side surface of the stack. Insulation and adhesive is located between the chips, and a wire contacting circuitry on one of the chips extends through the insulation to the side surface. A first conductor contacts the wire on the side surface. The first conductor is self-aligned to the wire and extends above the side surface. The first conductor facilitates pads or connectors on the side surface that are insulated from the semiconductor chips. The self-aligned first conductor is an electroplated or electroless plated metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.