Dual gate oxide formation with minimal channel dopant diffusion

US6030862A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventor

• Nick Kepler · Saratoga, US

Key dates

• Filing date: Oct 13, 1998
• Grant date: Feb 29, 2000
• Expiry date: Oct 13, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

Sharply-defined dopant profiles in the transistor channel region of ultra high density semiconductor devices are maintained by selective transistor channel implants to reduce exposure to heat cycling, thereby reducing dopant diffusion. Embodiments include forming isolation regions on a semiconductor substrate, forming a relatively thick first gate dielectric layer, then performing transistor channel implantations. The first gate dielectric layer is then masked and etched, and a second, thinner gate dielectric layer is formed. The transistor channel implants are not affected by the temperature cycle of the first gate dielectric layer formation, thereby enabling dual gate dielectric formation without adversely affecting the electrical characteristics of the finished device.