Reversed split-gate cell array
US6031765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this invention a reverse split gate device is described for creating a flash memory that avoids both programming and erase disturb conditions. The cell is designed so that the stacked gate is associated with the source and the enhancement gate is associated with the drain. This is the reverse of a conventional spit gate design and allows the drain to buffer the stacked gate from bit lines of a flash memory array. The source line now key to both program and erase operations is laid out in rows where two adjacent rows of cells share the same source line. The source line can be segmented to prevent the entire length of the pair of rows from being erased. The cell is programmed by flowing current backwards in the channel and injecting electrons in to the floating gate from an impact ionization that occurs near the source. Erasure is accomplished by Fowler-Nordheim tunneling from the floating gate to the source caused by a potential between the source and the enhancement gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.