Hierarchical decoding of a memory device
US6031784A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1998 |
| Grant date | Feb 29, 2000 |
| Priority date | — |
| Expiry date | Sep 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line for accessing a memory cell. A local word line driver, which drives the local word line, has at most two transistors, each of these transistors coupled to the local word line. In another aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line driver for driving a local word line. A local phase line driver is connected to the local word line driver by a single metal line. The local phase line driver cooperates with the local word line driver for accessing a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.