Wafer-level test and burn-in, and semiconductor process
US6032356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Apr 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.