Process for reducing copper oxide during integrated circuit fabrication
US6033584A · kind A · utility
71Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.