Multiple loadlock system
US6034000A · kind A · utility
31Cited by
27References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1997 |
| Grant date | Mar 7, 2000 |
| Priority date | — |
| Expiry date | Jul 28, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/908
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.