Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process

US6037216A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventors

• Hao Liu · Taizhou City, CN
• Fu-Liang Yang · Baoshan, TW
• Wan-Yih Lien · Hsinchu, TW
• Tzu-Shih Yen · Hsinchu, TW

Key dates

• Filing date: Nov 2, 1998
• Grant date: Mar 14, 2000
• Expiry date: Nov 2, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.