Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

US6040243A · kind A · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Jianxun Li · Singapore, SG
• Simon Chooi · Singapore, SG
• Mei Sheng Zhou · Singapore, SG

Key dates

• Filing date: Sep 20, 1999
• Grant date: Mar 21, 2000
• Expiry date: Sep 20, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76831
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.