Test head for integrated circuit tester arranging tester component circuit boards on three dimensions
US6040691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1997 |
| Grant date | Mar 21, 2000 |
| Priority date | — |
| Expiry date | May 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test head for an integrated circuit tester includes a horizontal base holding a motherboard. The motherboard distributes test instructions to an array of daughterboards mounted thereon, the daughterboards being radially distributed about a central vertical axis of the motherboard. Each daughterboard holds a set of node cards and includes data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the daughterboards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board. The interface board extends those conductive paths from the pads to terminals of the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.