EOS/ESD protection for high density integrated circuits

US6040968A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Charvaka Duvvury · Plano, US
• E. Ajith Amerasekera · Plano, US
• Sridhar Ramaswamy · Sunnyvale, US

Key dates

• Filing date: Jun 17, 1998
• Grant date: Mar 21, 2000
• Expiry date: Jun 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/60

Abstract

A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.