Method of integrating Ldd implantation for CMOS device fabrication
US6043533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Oct 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.