Digit line architecture for dynamic memory
US6043562A · kind A · utility
119Cited by
19References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 22, 1996 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Aug 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F.sup.2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.