Addressing scheme for a double data rate SDRAM
US6044032A · kind A · utility
127Cited by
9References
91Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. A unique addressing circuit controlled by an internal clock generates addresses for each plane from one external address. The generated addresses allow both planes to be accessed simultaneously. Thus, two sets of data from two independent planes of memory are simultaneously accessed in one system clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.