Wen Li
63Patents
19h-index
32Co-inventors
84Inventor score
Filing activity: Apr 15, 1996 → Oct 28, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6044032A | Addressing scheme for a double data rate SDRAM | Physics | 127 | Expired |
| US6691214B1 | DDR II write data capture calibration | Physics | 110 | Expired |
| US7138823B2 | Apparatus and method for independent control of on-die termination for output buffers of a memory device | Electricity | 79 | Expired |
| US6446180B2 | Memory device with synchronized output path | Physics | 71 | Expired |
| US6154418A | Write scheme for a double data rate SDRAM | Physics | 71 | Expired |
| US6381194B2 | OUTPUT CIRCUIT FOR A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY, METHOD OF CLOCKING DATA OUT FROM A DOUBLE DATA RATE DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF PROVIDING A DATA STROBE SIGNAL | Physics | 56 | Expired |
| US6240042A | Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal | Physics | 48 | Expired |
| US6763444B2 | Read/write timing calibration of a memory array using a row or a redundant row | Physics | 48 | Expired |
| US6438060B1 | Method of reducing standby current during power down mode | Physics | 46 | Expired |
| US6081477A | Write scheme for a double data rate SDRAM | Physics | 41 | Expired |
| US6704881B1 | Method and apparatus for providing symmetrical output data for a double data rate DRAM | Electricity | 38 | Expired |
| US7508384B2 | Writing system | Physics | 35 | Active |
| US5834813A | Field-effect transistor for one-time programmable nonvolatile memory element | Emerging Cross-Sectional Technologies | 26 | Expired |
| US5661428A | Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit | Physics | 23 | Expired |
| US6809990B2 | Delay locked loop control circuit | Physics | 23 | Expired |
| US6836437B2 | Method of reducing standby current during power down mode | Physics | 22 | Expired |
| US7165185B2 | DDR II write data capture calibration | Physics | 21 | Expired |
| US6480429B2 | Shared redundancy for memory having column addressing | Physics | 20 | Expired |
| US6922367B2 | Data strobe synchronization circuit and method for double data rate, multi-bit writes | Physics | 20 | Expired |
| US6968026B1 | Method and apparatus for output data synchronization with system clock in DDR | Electricity | 15 | Expired |
| US6532180B2 | Write data masking for higher speed DRAMs | Physics | 14 | Expired |
| US5886940A | Self-protected circuit for non-selected programmable elements during programming | Physics | 13 | Expired |
| US6259621A | Method and apparatus for minimization of data line coupling in a semiconductor memory device | Physics | 12 | Expired |
| US7054222B2 | Write address synchronization useful for a DDR prefetch SDRAM | Physics | 12 | Expired |
| US6694416B1 | Double data rate scheme for data output | Physics | 10 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.