Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6044429A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Jul 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.