Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias
US6046104A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | May 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Via void formation is substantially reduced or eliminated between the steps of depositing a barrier layer on a HSQ gap fill layer, and filling a through-hole with a conductive material deposited on the barrier layer, by performing a low-temperature baking following the deposition of the barrier layer. In particular, a high-temperature, low-pressure degas operation is performed immediately preceding, and in-situ with, the tungsten plug deposition that fills the through-hole to form a via. The low-pressure baking is performed at a high temperature and sufficiently low pressure that is less than the vapor pressure of imparities contained in the HSQ. Hence, any exposed portions of the HSQ gap fill layer that are not covered by the barrier layer (e.g., the titanium nitride (TiN) liner) will be outgassed during the low-pressure baking to minimize the possibility of HSQ outgas during tungsten deposition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.