High tensile nitride layer
US6046494A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1997 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.