Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM
US6046932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.