Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure
US6047352A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1996 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including an array of memory cells and a predecoding circuit operable to assert multiblock selection bits (for selecting two or more blocks of the cells simultaneously for simultaneous access) in response to control signals, and a method implemented by such a system, are disclosed. Preferably, the predecoding circuit is operable in a selected one of a first mode in which it asserts single block selection bits in response to address bits (each set of address bits determining one or more cells in a single block of the array) and a second mode in which it asserts multiblock selection bits stored in registers in response to control signals. In a write mode of one embodiment, each set of address bits is associated with a data byte to be written to cells in one row of one block, each set of multiblock selection bits is associated with cells in a row of each of two or more blocks, and the system writes the same data byte to multiple sets of cells (each set of cells in a different block) in response to each set of multiblock selection bits. Preferably, the predecoding circuit asserts a selected one of several different sets of multiblock selection bits in response to each o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.