Ferroelectric nonvolatile transistor and method of making same
US6048740A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Nov 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/701
Abstract
A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.