Method of manufacturing multilevel metal interconnect
US6048796A · kind A · utility
7Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.