Kun-Chih Wang
36Patents
11h-index
59Co-inventors
78Inventor score
Filing activity: Jun 13, 1997 → Jan 6, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6249073A | Device including a micromechanical resonator having an operating frequency and method of extending same | Electricity | 95 | Expired |
| US6046097A | Deposition method with improved step coverage | Electricity | 46 | Expired |
| US5976994A | Method and system for locally annealing a microstructure formed on a substrate and device formed thereby | Electricity | 42 | Expired |
| US6169321A | Method and system for locally annealing a microstructure formed on a substrate and device formed thereby | Electricity | 37 | Expired |
| US6900541B1 | Semiconductor chip capable of implementing wire bonding over active circuits | Electricity | 36 | Expired |
| US6080646A | Method of fabricating a metal-oxide-semiconductor transistor with a metal gate | Electricity | 26 | Expired |
| US6169028A | Method fabricating metal interconnected structure | Electricity | 22 | Expired |
| US6339025B1 | Method of fabricating a copper capping layer | Electricity | 19 | Expired |
| US6348398B1 | Method of forming pad openings and fuse openings | Electricity | 16 | Expired |
| US6013579A | Self-aligned via process for preventing poison via formation | Electricity | 12 | Expired |
| US7372168B2 | Semiconductor chip capable of implementing wire bonding over active circuits | Electricity | 11 | Expired |
| US7071575B2 | Semiconductor chip capable of implementing wire bonding over active circuits | Electricity | 11 | Expired |
| US7026234B2 | Parasitic capacitance-preventing dummy solder bump structure and method of making the same | Electricity | 10 | Expired |
| US10234905B2 | Hinge for foldable components | Electricity | 9 | Active |
| US7304385B2 | Semiconductor chip capable of implementing wire bonding over active circuits | Emerging Cross-Sectional Technologies | 8 | Active |
| US6048796A | Method of manufacturing multilevel metal interconnect | Electricity | 7 | Expired |
| US6080660A | Via structure and method of manufacture | Electricity | 7 | Expired |
| US6707129B2 | Fuse structure integrated wire bonding on the low k interconnect and method for making the same | Electricity | 6 | Expired |
| US5976984A | Process of making unlanded vias | Electricity | 6 | Expired |
| US7170167B2 | Method for manufacturing wafer level chip scale package structure | Electricity | 5 | Expired |
| US7208837B2 | Semiconductor chip capable of implementing wire bonding over active circuits | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6371045B1 | Physical vapor deposition device for forming a metallic layer on a semiconductor wafer | Electricity | 4 | Expired |
| US7147454B2 | Optical lens molding apparatus and precision molding apparatus | Emerging Cross-Sectional Technologies | 4 | Expired |
| US6710448B2 | Bonding pad structure | Electricity | 4 | Expired |
| US6245380A | Method of forming bonding pad | Electricity | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.