Semiconductor device having a metal containing layer overlying a gate dielectric
US6049114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Jul 20, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes providing a substrate (10) and depositing a gate dielectric (12) overlying the substrate (10). A gate is formed overlying the gate dielectric (12). The gate has a first sidewall and comprises a metal-containing layer (14) overlying the gate dielectric (12). A first spacer layer (20) is deposited over the gate and the substrate (10). A portion of the first spacer layer along the first sidewall forms a first spacer (22). A liner layer (30) is deposited over the gate and the substrate (10), and a second spacer layer (32) is deposited over the liner layer (30). The second spacer layer (32) is etched to leave a portion of the second spacer layer (32) along the first sidewall to form a second spacer (34). Also disclosed is a metal gate structure of a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.