Method and apparatus for generating memory addresses for testing memory devices
US6049505A · kind A · utility
12Cited by
4References
37Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 22, 1998 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.