Self-timed differential comparator
US6054918A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple-bit comparator achieves a fast operating speed and accurate operation through the connection of multiple individual-bit comparison devices to a first line and the connection of a timing device to a second line. The first line and the second line are differentially sensed to generate a signal designating whether all bits match or not. In some embodiments, the replica timing device is timed using a timing signal replicating the application of data to the individual-bit comparison devices and generates a signal on the second line that is delayed in comparison to the multiple-bit comparison signal on the first line by reduced sizing of the timing device in comparison to the individual-bit comparison devices. In some embodiments, a differential comparator includes a sense amplifier that is self-timed rather than utilizing a strobe signal to supply timing. In some embodiments, the sense amplifier includes a cross-coupled device that sources current between differential sides of the sense amplifier. A typical cross-coupled device supports a bias current, consuming power when the circuit is inactive. However, the present sense amplifier includes a precharge switch that stops cur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.