Memory cell
US6055177A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.