Electropolishing copper film to enhance CMP throughput
US6056864A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In-laid metal, e.g., copper or copper alloy, contacts and conductive routing patterns are formed in recesses in the surface of a substrate by a damascene-type process, comprising depositing a layer of an electrically conductive material filling the recesses and covering the substrate surface, reducing the thickness of the layer by a process providing a faster rate of layer removal than that obtained by chemical-mechanical polishing (CMP), and subjecting the remaining layer thickness to CMP processing to (a) substantially remove the remaining layer thickness and (b) render the exposed upper surface of the material filling the recesses substantially coplanar with the substrate surface, whereby increased manufacturing throughput, greater planarity, and reduced defects are obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.