DRAM structure with multiple memory cells sharing the same bit-line contact and fabrication method thereof
US6057187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
Abstract
The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.