Oxide etch stop techniques for uniform damascene trench depth
US6057227A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A damascene structure and method for forming such structure. In one embodiment, the damascene structure of the present invention includes a first layer of oxide which is a stochiometric oxide deposited onto a semiconductor substrate. A second layer of oxide which is a non-stochiometric oxide is then deposited onto the semiconductor substrate which is followed by a stochiometric oxide layer. The semiconductor substrate is then masked and etched so as to form vias using a selective etch process which etches the stochiometric oxide and stops etching on the non-stochiometric oxide layer. The etch chemistry is then changed in-situ, allowing the removal of the non-stochiometric oxide at the bottom of the via. The wafer is then re-masked in the pattern of trench interconnect using a selective etch process to selectively etch the layer of stochiometric oxide in the damascene trench down to the layer of non-stochiometric oxide while simultaneously completing the etching of vias. The use of the layer of non-stochiometric oxide as an etch stop gives trenches with a substantially planar bottom surface in a process superior in simplicity and process margin compared to nitride etch stop technolo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.