Semiconductor device having a tri-layer gate insulating dielectric
US6057584A · kind A · utility
25Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.