System and method for generating effective layout constraints for a circuit design or the like
US6058252A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Aug 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system and computer implemented method for deriving constraints with which to direct automatic integrated circuit layout is disclosed. The present invention is particularly adapted for use in the design of large integrated circuits with complex synchronous timing behavior. Preferably, the invented computer system includes means for storing a netlist data structure within a storage means is provided, the netlist data structure representing a circuit configuration having a plurality of circuit elements and representing static timing information for the circuit configuration; means for selecting specified circuit elements to be used for generating the layout constraints, whereby the specified circuit elements that are selected are fewer than, i.e. represent a proper subset of, the plurality of circuit elements of the circuit configuration; means for identifying a most critical path through each of the specified circuit elements based upon the static timing information, whereby preferably the most critical path is that path having the least slack defined as the difference between a required time at which a signal should reach the specified circuit element and an arrival time…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.