Specialized millicode instruction for translate and test
US6058470A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Apr 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a millicode operating in a milli-mode state when macro-mode decoding by said processor is suspended to cause the system to subsequently use processor milli-registers and the processor's decoder decodes them and schedules them for execution upon entry into the processor milli-mode. Millicode flags allow specialized update and branch instructions and flags are either cleared or specifically set for a millicode instruction. A millicode instruction for editing functions processes one byte of an input pattern string, generates one byte of an output string, and updates various pointers and state indications to prepare for processing the next byte in a string. Translate Fetch (TRFET) millicode instructions support a Translate and Test TRT instruction and specialized millicode instructions for packed decimal division make use of the hardware control and dataflow logic de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.