Methods for forming a control gate apparatus in non-volatile memory semiconductor devices
US6063662A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
Methods are provided to increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device. The methods effectively smooth out the top surface of the control gate layer, which allows for a subsequently formed silicide layer to be formed on the control gate layer without significant surface depressions. Significant surface depressions in either the control gate layer or the silicide layer can lead to cracking of the silicide layer during subsequent thermal processing of the semiconductor device. Thus the disclosed methods prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.