Method for forming high voltage device
US6063674A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Oct 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second P-well are formed in the P-type semiconductor substrate. A first N-well is formed in the second p-well and a second N-well is formed in the first P-well. A field oxide layer on the second N-well and a gate oxide layer are formed on the P-type substrate. A polysilicon layer is formed and defined as a gate on the gate oxide layer across a portion of the field oxide layer and aportion of the first N-well. A source region is formed in the first N-well and a drain region is formed in the second N-well. A P.sup.+ -type doped region is formed between the substrate and the source region across a part of the first N-well within the second P-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.