Method and apparatus for preventing formation of black silicon on edges of wafers

US6066570A · kind A · utility

Assignees

• Siemens Aktiengesellschaft · DE
• International Business Machines Corporation · US

Inventors

• Dung-Ching Perng · San Jose, US
• David M. Dobuzinsky · New Windsor, US
• Ting Wang · White Plains, US
• Klaus Roithner · Aßling, DE

Key dates

• Filing date: Dec 10, 1998
• Grant date: May 23, 2000
• Expiry date: Dec 10, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3081
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.