Delayed locked loop implementation in a synchronous dynamic random access memory
US6067272A · kind A · utility
34Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.