Adjustable output driver circuit having parallel pull-up and pull-down elements
US6069504A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Sep 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.