Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction
US6070238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1997 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Sep 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One aspect of the invention relates to a super scalar processor having a memory which as addressable with respect to the combination of a page address and a page offset address, and provides a method for detecting an overlap condition between a present instruction and a previously executed instruction, the previously executed instruction being executed prior to execution of the present instruction. In one embodiment, the method comprises the steps of dividing the present instruction into a plurality of aligned memory accesses; determining the page offset for at least one of the aligned accesses; and comparing the page offset and byte count for the present instruction to a page offset and byte count for the previously executed instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.