Vertical DMOS field effect transistor with conformal buried layer for reduced on-resistance

US6072216A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Wayne B. Grabowski · Los Altos, US

Key dates

• Filing date: May 1, 1998
• Grant date: Jun 6, 2000
• Expiry date: May 1, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell. The dopant penetrates less deeply into the epitaxial layer under the thick oxide layer, and this yields the "conformal" shape of the buried layer. Alternatively, the buried layer can be formed with two implants, i.e., by forming a horizontal buried la…