Nonvolatile reprogrammable interconnect cell with programmable buried bitline
US6072720A · kind A · utility
8Cited by
1References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.