Memory system having flexible architecture and method
US6073204A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Apr 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0676
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.