Self-aligned processing of semiconductor device features
US6074921A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique for self-aligned processing of semiconductor device features is disclosed. This technique includes the formation of a semiconductor device with features extending from the plane of a semiconductor substrate. The features may include polysilicon transistor gates. A coating is deposited on the features and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a surface of the features without lithographic processing. In one form, the exposed surface of the feature is defined by a polysilicon member, and the polysilicon member is at least partially selectively removed and replaced with a metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.