Integrated, multi-chip, thermally conductive packaging device and methodology
US6075287A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Apr 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electrically conductive lamina are attached by an electrically insulating, thermally conductive adhesive and/or solder to one or more semiconductor devices such as chips and extend beyond the periphery of the chip or chips to form heat sink fins. Electrical connections may be made between such chips through holes (e.g. by a wire or plated through hole) in the electrically conductive lamina lined with an insulating material such as the electrically insulating adhesive to provide a structurally robust assembly. Surface pads and connections may overlie patterns of insulator on the lamina. A further lamina can be wrapped around lateral sides of the assembly to provide further heat sink area and mechanical protection for other heat sink fins. A graphite/carbon fiber composite matrix material is preferred for the lamina and the coefficient of thermal expansion of such materials may be matched to that of the semiconductor material attached thereto. Conductivity of the lamina also provides shielding against electrical noise to improve the noise immunity of short connections between chips made through the lamina as well as that of surface connections which may be formed on the lamina.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.