High performance cost optimized memory with delayed memory writes
US6075730A · kind A · utility
151Cited by
6References
6Claims
0Family size
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Key dates
| Filing date | Oct 9, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.