Circuits and methods for selectively coupling redundant elements into an integrated circuit
US6077211A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for selectively coupling redundant components into an integrated circuit. Global I/O lines are coupled to local I/O lines through a number of multiplexors. Bitlines are grouped into blocks of bitlines. A fuse bank couples to the number of multiplexors through a logic/select circuit. When at least one fuse's state indicates that the associated I/O line is inoperable, the logic/select circuit switches the coupling to connect the global I/O line with a redundant local I/O line. The redundant local I/O's are configured to access the original block of bitlines. The arrangement conserves precious chip space and preserves uniform timing between normal and redundant data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.