Modified implementation of air-gap low-K dielectric for unlanded via
US6077767A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a multilevel interconnect, where a first and a second conducting wires are formed respectively on a substrate, while a part of the substrate between the first and the second conducting wires is exposed. A first dielectric layer is then formed to cover the substrate as well as the first and the second conducting wires, wherein the first dielectric layer has an air gap formed between the first and the second conducting wires. An anti-etch layer is formed on the first dielectric layer above the air gap, while a second dielectric layer is then formed on the anti-etch layer and the first dielectric layer. A via opening which exposes the first conducting wire is then formed by etching, followed by forming a barrier layer which covers the profile of the via opening and the exposed surface of the first conducting layer. Consequently, a via plug is formed to fill the via opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.