Force applying probe card and test system for semiconductor wafers
US6078186A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; an interconnect slidably mounted to the substrate; and a force applying mechanism for biasing contacts on the interconnect into electrical engagement with contacts on the wafer. The force applying mechanism includes spring loaded electrical connectors that provide electrical paths to the interconnect, and generate a biasing force. The biasing force is controlled by selecting a spring constant of the electrical connectors, and an amount of Z-direction overdrive between the probe card and wafer. The probe card also includes a leveling mechanism for leveling the interconnect with respect to the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.